The following commonly assigned patent/patent applications are hereby incorporated herein by reference:
The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of forming a silicide region.
Titanium silicide has become the most widely-used silicide in the VLSI industry for self-aligned silicide applications because of its combined characteristics of low resistivity, the ability to be self-aligned, and relatively good thermal stability. Although TiSi2 has certain advantages relative to other silicides, the fact that it is a polymorphic material presents additional problems in its use. Specifically, in typical use TiSi2 exists as either an orthorhombic base-centered phase having 12 atoms per unit cell and a resistivity of about 60-90 micro-ohm-cm (known in the industry as the C49 phasexe2x80x94see FIG. 1), or as a more thermodynamically-favored orthorhombic face-centered phase which has 24 atoms per unit cell and a resistivity of about 12-20 micro-ohm-cm (known as the C54 phase). When using the generally-accepted processing conditions for forming titanium silicide, the less-desirable, higher-resistivity C49 phase is formed first. In order to obtain the lower-resistivity C54 phase, a second high-temperature temperature annealing step is required. This second step is disadvantageous because it can have detrimental effects on the silicide and other integrated circuit elements, especially at smaller line-widths. For example, the increasing use of dual-doped polysilicon gate structures in some devices has increased their sensitivity to additional heat cycles, as is required by the second anneal step. Also, silicon nitride peeling and cracking have been associated with the second annealing step. Furthermore, the second anneal step increases PMOS source and drain series resistances, thereby degrading (i.e. decreasing) the device drive current.
A typical set of processing conditions for forming titanium silicide include: (1) pre-cleaning, (2) titanium deposition, (3) silicide formation at a temperature about 700xc2x0 C., (4) selective etching, and (5) a phase transformation anneal at a temperature greater than about 700xc2x0 C. It is the phase transformation anneal that converts the dominant C49 phase to the C54 phase. The initial formation temperature is kept about 700xc2x0 C. or below in order to minimize over-spacer bridging. The second transformation anneal is performed after any unreacted titanium has been selectively removed and is generally performed at temperatures of 50xc2x0-200xc2x0 C. above the formation temperature to insure full transformation to the C54 phase for best control of sheet resistance. However, as device line-widths and silicide film thickness continue to be scaled down, it becomes ever more desirable to eliminate the need for this second anneal step, as discussed further below.
It is generally accepted that the C49 phase forms first because of a lower surface energy than that of the C54 phase. In other words, the higher surface energy of C54 phase forms a higher energy barrier to its formation. The second transformation anneal step used in the standard process above provides the additional thermal energy necessary to both overcome the nucleation barrier associated with forming the new surface and growing the crystalline structure of the newly-forming C54 phase. In VLSI applications, if the phase transformation is inhibited or fails to occur uniformly, a degradation in circuit performance is observed. In some higher-performance circuits, the RC delay associated with a poor phase transformation is typically about 5-10 percent.
A significant limitation on the C49-to-C54 phase transformation is a phenomenon known as agglomeration. If the thermal energy used to obtain the phase transformation is excessive, then a morphological degradation of the titanium silicide results, which is commonly referred to as agglomeration. As line-widths and silicide film thickness decrease, the thermal energy required to affect the C49-to-C54 phase transformation increases, yet the thermal energy level at which the silicide film starts to agglomerate decreases. Thus, there is an ever-shrinking process window for performing this phase transformation, making process control and uniformity more difficult to achieve.
Thus, there is a need for an improved method for forming the C54 phase titanium silicide without requiring a second high-temperature annealing step, as in the generally-accepted process above. Eliminating the second annealing step would reduce the problems and limitations resulting from agglomeration of silicide films during the phase transformation anneal.
One solution to this problem was introduced in U.S. Pat. No. 5,510,295. The solution introduced in this patent involves either depositing a xe2x80x9crefractory metalxe2x80x9d and a xe2x80x9cprecursory metalxe2x80x9d on a silicon layer simultaneously or putting the xe2x80x9crefractory metalxe2x80x9d into the silicon layer followed immediately by depositing the xe2x80x9cprecursory metalxe2x80x9d on the silicon layer. While this method facilitates the formation of the low resistivity silicide layer (i.e. C54 phase TiSi2), this method has a few problems.
In a related published article, a method is detailed for putting molybdenum or tungsten between single-crystal or polycrystalline silicon and the titanium layer so as to reduce the temperature of subsequent anneals steps so as to transform to the C54 phase silicide. See R. W. Mann et al., Reduction of the C54-TiSi2 Phase Formation Temperature Using Metallic Impurities, Silicide Thin Filmsxe2x80x94Fabrication, Properties, and Applications 95-100 (Nov. 27-30, 1995). The implantation of molybdenum (xe2x80x9cmolyxe2x80x9d) into the single-crystal silicon substrate or polycrystalline silicon (xe2x80x9cpolyxe2x80x9d) overlayer causes xe2x80x9cvery few crystalline defects and no amorphous regionsxe2x80x9d in these regions for the method of this publication. Hence, this publication only relates to the lowering of the annealing temperature required to transform a titanium silicide layer into its C54 phase by the implantation of moly into silicon regions (followed by an anneal to eliminate any defects introduced by the implant) prior to deposition and annealing of the titanium layer. As was discussed above, this method suffers from the same deficiencies as U.S. Pat. No. 5,510,295.
While the two aforementioned processes achieve low sheet resistance silicide regions formed on the gate structures, these processes do not form low sheet resistance silicide regions on the source/drain regions. The reaction of the titanium with polycrystalline silicon may form low resistivity C54 phase TiSi2 in the presence of molybdenum impurities in these processes. However, using the same process, the C49 phase TiSi2 will form on single crystal silicon (100). This is illustrated in FIGS. 2(a) and 2(b). FIG. 2(a) illustrates the TiSi2 formed on polycrystalline silicon using one of the two aforementioned prior art processes, and FIG. 2(b) illustrates the silicide formed on single crystal silicon (using the same process).
Another problem with the two aforementioned processes is that it is difficult to form silicide regions with low sheet resistance on gate structures that have a gate length of less than 0.1 microns.
Basically, the method of the instant invention overcomes this problem by amorphizing a top portion of the gate structure and/or the source/drain regions so that the lower resistivity silicide readily forms in these regions.
An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming a conductive structure insulatively disposed over the semiconductor substrate; introducing a silicide enhancing substance into the conductive structure; amorphizing a portion of the conductive structure; forming a metal layer on the conductive structure; and wherein the metal layer interacts with the silicide enhancing substance in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure. The conductive structure is, preferably, comprised of: doped polysilicon, undoped polysilicon, epitaxial silicon, or any combination thereof. Preferably, the silicide enhancing substance is comprised of: molybdenum, Co, W, Ta, Nb, Ru, Cr, any refractory metal, and any combination thereof. The metal layer is, preferably, comprised of: titanium, Co, W, Mo, nickel, platinum, palladium, and any combination thereof.
In another embodiment of the instant invention, the method further includes the step of performing a low temperature anneal step after the step of forming a metal layer on the gate structure. Preferably, the low temperature anneal step is comprised of subjecting the transistor to temperatures in excess of 600 C. (more preferably, around 700 to 800 C.).
Preferably, the step of amorphizing a portion of the conductive structure is accomplished by introducing an amorphizing substance into the conductive structure. The amorphizing substance is, preferably, comprised of: As, Ge, or any combination thereof.
In another embodiment of the instant invention, the step of forming a conductive structure is comprised of the steps of: forming a semiconductive layer insulatively disposed over the semiconductor substrate; doping the semiconductive layer; and etching portions of the semiconductive layer so as to form the conductive structure. Preferably, the step of introducing the silicide enhancing substance is performed prior to the step of etching portions of the semiconductive layer; or it is performed after the step of etching portions of the semiconductive layer so that the silicide enhancing substance is introduced into the conductive structure and source/drain regions formed in the semiconductor substrate.
In another embodiment of the instant invention, the method further includes the steps of: introducing source/drain dopants into the semiconductor substrate in locations which are adjacent to the conductive structure; and performing a source/drain anneal step at an elevated temperature. The step of amorphizing a portion of the conductive structure is, preferably, performed after the step of performing a source/drain anneal step. The portion of the semiconductor substrate where the source/drain dopants are introduced may or may not be amorphized during the step of amorphizing a portion of the conductive structure. In an alternative embodiment, the step of introducing a silicide enhancing substance into the conductive structure is comprised of depositing a layer of the silicide enhancing substance over at least a portion of the semiconductor substrate and the conductive structure and reacting the layer of silicide enhancing substance with the conductive structure.